This application claims priority to Korean Patent Application No. 2001-35424, filed on Jun. 21, 2001, which is commonly owned and incorporated by reference herein.
1. Technical Field
The present invention relates to a semiconductor memory device and, more particularly, to a method for an erase operation in a non-volatile semiconductor memory device.
2. Description of Related Art
Generally, non-volatile electrically erasable and programmable read only memories (EEPROMs) are classified into floating gate EEPROMs and polysilicon-blocking oxide-silicon nitride-tunnel oxide-semiconductor (SONOS) EEPROMs.
EEPROMs store data in a floating gate of polysilicon or entrap data in a nitride layer while increasing or decreasing a threshold voltage to perform a program (or write) operation. When reading the stored data, EEPROMs use a sensing circuit to apply a read voltage (Vr) and sense a current flowing to a channel. Also, to perform an erase operation, EEPROMs remove the stored data in the polysilicon or the nitride layer.
In SONOS EEPROMs, a read operation is performed when stored data is varied. Accordingly, the stored data must be completely removed throughout a channel to secure reliability of the device. Otherwise, the read and erase operations are repeatedly performed to accumulate data continuously, and the read operation can be erred by the varying of a threshold voltage.
FIG. 1 is a cross-sectional view showing a memory cell according to a conventional program method in a SONOS EEPROM device. FIG. 2 shows a memory cell according to a conventional erase method in a SONOS EEPROM device. FIG. 3A shows a memory cell according to another conventional erase method in a SONOS EEPROM, and FIG. 3B illustrates a waveform of the voltages applied to the memory cell of FIG. 3A. In FIG. 3B, a traverse axis represents time (t), and a longitudinal axis represents applied voltages.
Referring to FIG. 1, a memory cell 50 comprises a P-type bulk region 10, spaced drain and source regions 12, 14 formed in the P-bulk region 10, a channel region 13 formed between the drain and source regions 12, 14, an ONO layer 22 (comprising a tunnel oxide 16, a nitride 18, and a blocking oxide 20 layer) formed on the channel region 13, and a polysilicon gate electrode 24 formed on the ONO layer 22. To program the memory cell, the drain and source regions 12, 14 and the P-bulk region 10 are grounded through a metal contact and a program voltage Vpp is applied to the gate electrode 24. And, electrons are entrapped in the nitride layer 18 through a thin tunnel oxide layer 16 by F-N tunneling (Follower-Nordheim tunneling).
In a conventional erase method shown in FIG. 2, a negative program voltage xe2x88x92Vpp is applied to a gate electrode 24 with the drain and source regions 12, 14 and a P-bulk region 10 being grounded. Holes are then injected from the P-bulk region 10 to a tunnel oxide layer 16 and a nitride layer 18, compensating the entrapped electrons in the program operation to perform the erase operation. Unfortunately, it is difficult to form and apply the negative voltage xe2x88x92Vpp to the gate electrode 24.
A memory cell according to another conventional erase method, shown in FIG. 3A, further comprises a pocket P-well 11 formed in the N-bulk region 10. In an erase operation, the gate electrode 24 is grounded, and an erase voltage Vpp is applied to the drain and source regions 12,14, the pocket P-well 11, and the N-bulk region 10 through a metal contact. The applied voltages are schematically shown in FIG. 3B. One disadvantage associated with the memory device in FIG. 3A is that the pocket P-well 11 must separately be formed, thus increasing the complexity and processing costs.
Although not shown in FIGS. 1-3, another conventional erase method can be performed by grounding a gate electrode and the bulk region, and equivalently applying an erase voltage to source and drain regions. In the erase method, a high-energy hole (so-called xe2x80x9chot holexe2x80x9d), formed at both sides (i.e., source and drain regions) of a channel, is vertically injected through a source region-to-gate electrode junction side and a drain region-to-gate electrode junction side. However, the erase method cannot fully perform the erase operation at the center of the channel. Therefore, the entrapped electrons are not removed and are continuously accumulated in a nitride layer over the channel center. As a result, a threshold voltage is heightened and a sensing margin is reduced.
Thus, a need exists for a circuit framework that generates a negative voltage without occupying additional area in a semiconductor device.
It is therefore an object of the present invention to provide an efficient erase method in a non-volatile semiconductor memory device capable of achieving a reliable erase operation throughout a channel region, which does not require applying a negative voltage or performing a pocket well process.
According to one aspect of the present invention, a non-volatile memory device is provided which enables an effective erase operation according to the invention. The device comprises a bulk region of a first conductive type, spaced first and second impurity diffusion regions of a second conductive type formed in the bulk region, a charge storing layer formed between the first and the second impurity diffusion regions, and a conductive electrode formed on the charge storing layer. The method for performing an erase operation in the non-volatile memory device comprises the steps of: applying a bulk voltage to the bulk region for a predetermined erase time; applying a gate voltage to the conductive electrode for the predetermined erase time, the gate voltage being greater than or equal to the bulk voltage; applying a first electrical signal to the first impurity diffusion region for the predetermined erase time, the first electrical signal comprising a voltage that is greater than the gate voltage; and applying a second electrical signal to the second impurity diffusion region for the predetermined erase time, the second electrical signal comprising a voltage that is greater than the gate voltage, wherein the voltage of the first electrical signal is different from the voltage of the second electrical signal.
The voltage level of the first electrical signal is switched between a first voltage and a second voltage at least one time, during the predetermined erase time, wherein the first and second voltages are greater than the gate voltage. The second electrical signal is substantially equal to the first and second voltages when the first electrical signal is substantially equal to the second and the first voltages, respectively for the predetermined erase time. For example, the first voltage ranges from about 2V to about 6V, and the second voltage is about 10V.
According to another aspect of the present invention, a method for performing an erase operation in a memory cell, comprising a bulk region of a first conductive type, spaced source and drain regions of a second conductive type formed in the bulk region, and a gate electrode formed between the source and drain regions is provided. The method comprises the steps of: applying a first voltage to the source region and a second voltage to the drain region for a portion of a predetermined erase time; and applying the second voltages to the source region and the first voltage to the drain region for a portion of the predetermined erase time.
According to further aspect of the present invention, a method for performing an erase operation in a non-volatile memory device, comprising a bulk region of a first conductive type, spaced source and drain regions of a second conductive type formed in the bulk region, and a gate electrode formed between the source and drain regions, is provided. The method comprises the steps of: applying a first voltage and a second voltage to the source and drain regions, respectively, for a predetermined erase time; applying a third voltage to the gate electrode, wherein the potential differences between the third voltage and the first and second voltages are sufficient to generate electric fields between the gate electrode and the source and drain regions to inject holes into the source and drain regions, respectively; and switching the first voltage to the drain region and the second voltage to the source region at least one time during the predetermined erase time.
Advantageously, according to the present invention, by applying and switching different voltage levels to source and drain regions, respectively for predetermined erase time, hole is easily injected into the source and drain regions, and a channel lateral surface. Therefore, it is possible to achieve uniform and high-speed erase operation.
These and other objects, aspects, features, and advantages of the present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.